Published: February 25, 2018
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By: Chenglin Ma, Cal Poly Pomona
Hardware Team Member
• Designed and Generate the PL on the PL side of MicroZed 7020.
• Designed Quadrature Decoders and Servo Interfacing on HDL.
• Designed Universal Asynchronous Receiver/Transmitter (UART).
• Designed Circular based Queue FIFO Buffer in order to improve UART performance.