In the Lab, I built the circuit as same as the schematic in the proposed schematic, but the overall gain was about 500 because the values of resistors in Lab were not the same as the values in Pspice (small changes in the resistors could affect the overall gain). In the requirement, Vout_noload should be 4V Pk-pk, so a 10V DC power supply was enough to power 4 stages. The first stage is the common emitter with a bypass capacitor in parallel with the emitter resistor to get a high gain of 100; without the capacitor, the gain would depend on the values of RC and RE , Gain RC/RE = 10.5k/1k10 and if I increased the RC value, the gain would be increased, but I could not keep increasing the RC to get the high gain. I decided to use a bypass capacitor to reach a high gain which depends much on internal RC and re’ , the gain will be |A_vi |=RC/re’ because the re’ value is too small. The capacitor also had another purpose which is used for creating the lower cut-off frequency to be less than 50 Hz. The second stage has the voltage follower, is used for holding stage 1 gain because of a high input impedance characteristic. The third stage-common emitter amplifier, I didn't use a bypassed capacitor at the emitter anymore because I just need a small gain to reach an overall gain of 400, again the Gain of the common emitter RC/RE. When I did the prelab, I tried putting a RC=4K and RE=1K, but the gain I got was much lower than 4 which could affect the overall gain of 400. So I adjusted the value of RE up to 7K(Prelab) and 6.11K(Lab) to get a gain 4. The final stage was the same as stage 2 which was the voltage follower with the gain 1; I decided to use the voltage follower for the final stage because the output of the voltage folower is small that would meet the lab requirement impedance< 50 Ω. I though about decreasing the emitter resistor 220 Ω in stage 4 to meet the output of 2V pk-pk withload; however, if I did that, the overall gain without load would be dropped as well. Finally, the overall gain I got =stage 1*stage2*stage3*stage4=(-100)*1*(-4)*1400. Other than the gain_withload and the input impedance issue, this new design worked perfectly, and it met almost all the goals.
The circuit specification: Av=400, Rin> 10k, Rout< 50, f(low)< 50Hz, f(high)> 75kHz