Implementation of The FIR using VHDL and FPGA
Like Chenglin Ma

Implementation of The FIR using VHDL and FPGA

Implementation of The FIR using VHDL and FPGA

Description:

Published: October 27, 2018 0 0 36
By: Chenglin Ma, Cal Poly Pomona
Category: Engineering

Constructed a full ADC to DAC system, ADC was used ARTIX-7 X_ADC core internal 12-bit analog to digital converter, and output DAC was AD5628 external chip. Implemented a FIR Low-pass filter in this system, by using MATLAB to calculate the coefficients and simulate the results of the filter.
The system was demonstrated with 1-volt peak to peak sinusoid wave at various frequencies.
Well-practiced how to use VHDL to implement an ADC and DAC system in FPGA.
Learned how to implement filters in FPGA by using VHDL with the help of MATLAB and Simulink.

Attachments:

Labreport_final.docx 671.2 KB

Tagged Teammates:

  • Gage Ramlose
  • Sunny Wang