Published: June 24, 2019
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By: Quyen Nguyen, Cal Poly Pomona
This project’s objective is to design a model that computes the Greatest Common Divisor (GCD) of two numbers . The algorithm for this model will be the same as the given golden model which is a C-like Verilog code. These two models will be compared to see how using clock affect the execution of the algorithm in our design. This model will combine a data path unit and a control unit that are connected with each other. The data path unit will consist of hardware such as registers, counters, multiplexers… The control unit will consist of a finite state machine that helps moving the data through the data path unit. The two unit are connected to each other by using control words. Waveforms for the two models will be generated to see how many clocks cycles each model take to create the same results. After running the simulation for the two models, our designed model will be implemented using a FPGA board to see how the design actually work in hardware by using a top-level module that includes a frequency divider, binary to bcd converter, and a bin2seg to display on the seven segment of the FPGA board.