FIFO Buffer
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FIFO Buffer

FIFO Buffer

Description:

Published: January 4, 2021 0 0 29
By: Arturo Murillo, California State Polytechnic University-Pomona
Category: Engineering
Hashtags: #CalPoly #CalPolyPomona #Design #Electrical #Engineering #Project #Teamwork

This project involved the use of a FIFO buffer in a Nexys 4 FPGA. The FIFO can store up to 4 bytes but is parametrized to take more bytes. The input voltage from the Xadc (potentiometer) determines what bytes will be push after a button is a press. To read from the FIFO, we find the sum of all the stored bytes. Finally, we display the empty and full flags using two LEDs. I also added other functionalities show in the video. To view the code, my GitHub account is in the next slide.