180nm TSMC NMOS and PMOS Simulation
Like Nirupam Saha

180nm TSMC NMOS and PMOS Simulation

180nm TSMC NMOS and PMOS Simulation

Description:

Published: November 21, 2020 0 0 7
By: Nirupam Saha, Cal Poly Pomona
Category: Electrical Engineering

This project demonstrates the non-ideal effects on TSMC 180nm NMOS and PMOS devices. For this demonstration, we simulated these devices and obtained the IDS vs VDS plots which were compared to the hand-calculated values. To obtain the simulations, we used the software LtSpice which allowed us to specify the models for TSMC 180nm NMOS and PMOS with specified device width and length of 0.3µm and 0.18µm, respectively. We also specified other device features such as the version, TNOM, TOX, etc. using a provided string of model specifications which was copied into an LtSpice directory. Next, a nested .DC sweep analysis was done at the VDD source for three predetermined VGS values to create a simulation of IDS vs VDS plots, and the results were compared with hand-calculated values. As the simulated plots indicate, the obtained IDS values in the simulation were in fact lower compared to the hand calculated values as expected due to non-ideal effects such as mobility degradation and velocity saturation.