Member Since October 24, 2017
3-bit counter using Verilog on FPGA
3-bit counter written in verilog HDL implemented on the basys3 FPGA board
Sign Magnitude Adder using Verilog on FPGA
FPGA project written in verilog HDL to implement a Sign Magnitude Adder on the Basys3 FPGA board. Information...
3-8 Decoder to 7-segment display using Verilog
FPGA project written in verilog HDL to implement a 3-8 decoder which connects to a 7-segment display...